// tb_top.sv
// 验证套件
`timescale 1ns/1ps
module tb_top;

  // 时钟与复位
  logic clk, rst_n;
  initial begin
    clk = 0;
    forever #2.5 clk = ~clk;  // 200 MHz
  end
  initial begin
    rst_n = 0;
    #20 rst_n = 1;
  end

  // DUT 实例化
  riscv_npu_soc dut (
    .clk(clk),
    .rst_n(rst_n),
    .tck(1'b0), .tms(1'b0), .tdi(1'b0), .tdo(),
    .apb_paddr(32'd0), .apb_psel(1'b0), .apb_penable(1'b0),
    .apb_pwrite(1'b0), .apb_pwdata(32'd0),
    .apb_prdata(), .apb_pready(), .apb_pslverr()
  );

  // 接口
  riscv_npu_if vif(clk, rst_n);
  assign vif.mem_req   = dut.u_top.core_mem_req;
  assign vif.mem_we    = dut.u_top.core_mem_we;
  assign vif.mem_addr  = dut.u_top.core_mem_addr;
  assign vif.mem_wdata = dut.u_top.core_mem_wdata;
  assign dut.u_top.core_mem_rdata = vif.mem_rdata;
  assign dut.u_top.core_mem_ack   = vif.mem_ack;

  // UVM 配置
  initial begin
    uvm_config_db#(virtual riscv_npu_if)::set(null, "*", "vif", vif);
    run_test();
  end

  // 覆盖率
  `include "npu_covergroups.sv"
  npu_coverage cov_inst(.vif(vif));

endmodule